Samsung Electronics has confirmed it is developing DRAM based on 4F2 Vertical Channel Transistor (VCT) architecture, a technology designed to fit more memory capacity into the same silicon area. The effort comes as Chinese memory maker Changxin Memory Technology (CXMT) says it aims to launch server DRAM using the same architecture by the end of 2026.
Song Jae-hyuk, Samsung Electronics’ chief technology officer, confirmed the company’s 4F2 work at the SEDEX 2026 exhibition in Seoul. CXMT’s earlier announcement had raised investor concerns over the pace of progress among Chinese memory-chip suppliers, while demand for memory used in AI servers continues to expand.
Conventional DRAM places its memory cells primarily in a horizontal layout, making further density gains increasingly difficult as transistor dimensions shrink. A vertical-channel design reduces the footprint of each cell. In 4F2, the name refers to a theoretical cell area equal to four times the square of the minimum fabrication feature size, potentially enabling higher-capacity chips without increasing their physical dimensions.
The approach could be an intermediate step toward 3D DRAM, where memory cells are stacked across multiple layers in a model similar to NAND flash. Samsung is also exploring zHBM for faster data transfers in AI systems and zNAND-O for high-performance storage. It has not announced a commercial-production timetable for 4F2 VCT DRAM, leaving CXMT’s planned 2026 server-memory launch as the nearest stated milestone in this emerging contest.
